Standardized Enumeration of FPGAs

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One Line Summary

Existing and emerging mechanisms for enumerating FPGAs


We discuss the existing mechanisms for enumeration of FPGA and programmable logic devices, as well as the interconnects in use. A trend toward coherently attached logic devices that appear as “fake PCIe” is emerging, and each of the co-presenters will speak about work being done within the community for their architecture to support these different choices.


FPGA, enumeration, probing


  • Biography

    Jon Masters is Chief ARM Architect at Red Hat and also involved in various efforts to standardized FPGA and programmable logic

  • Zach Pfeffer

    Audience, Inc.


    I am currently the Director of Host Software at Audience, Inc. Audience’s goal is to be the ears of every device.

    Prior to Audience, I was the Android Platform Lead at Linaro. During my time there I lead an extremely talented group of engineers who maintained and released Linaro Android platforms on the Pandaboard, Exynos, Snowball and other boards. The unique thing about our builds was that they were built with the tip of GCC, the tip kernel and the latest Android source from AOSP. I am still in awe of what the team accomplished and continues to accomplish.

    Prior to Linaro, I helped Polycom build Android based video conferencing endpoints, helped Qualcomm maintain and release their Android kernel. I also helped Google build and release the first Android devices: the G1 and the Nexus One. Previous to Android work I built a whole mess of software for a pulse pattern generator at Picosecond Pulse Labs in Boulder Colorado, my home town. Go Buffs!

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    Alan Tull



    I’ve been writing Linux device drivers for 17 years, at Cirrus Logic, Freescale, Altera, and now Intel.

    I wrote the FPGA Manager framework which is in the upstream kernel and have proposed Device Tree Overlays support for programming FPGAs.