Localising the system latency/throughput/power tunability surface

Session information has not yet been published for this event.


One Line Summary

Discussion on enabling per-task tuning of kernel policies using a well defined user-space interface


The topic of a single simple power-performance tunable, that is wholly scheduler centric, with defined and predictable properties, has come up on several occasions in the past.
With frameworks such as schedutil being recently merged, we now have a suitable base for implementing such a tunable.

This presentation introduces the foundation to add a single, central tunable ‘knob’ to the scheduler. The main goal is to present an initial proposal for a possible solution as well as to collect feedback and suggestions for a better user-space interface which is both useful and efficient.


performance, power, scheduler, PELT, schedutil, WALT

Presentation Materials



  • Pb_goldengate

    Patrick Bellasi

    ARM Ltd


    Patrick Bellasi is a Senior Software Engineer at ARM Ltd (Cambridge) working as a Linux scheduler specialist on Energy Aware Scheduling for ARM big.LITTLE technology.

    He developed the EAS ‘SchedTune’ extension to provide per-task energy-vs-performance tuning which has been merged into the Android Common Kernel. He is also responsible for configurable tooling (LISA, BART, TRAPpy) used to analyse scheduler behaviour in product applications.

    Previously, Patrick has been a Post-Doc at Politecnico di Milano, working in cooperation with STMicroelectronics in different projects related to SoCs energy optimization and run-time resource management of experimental many-core architectures.